`timescale 1 ns / 1 ps

module top;
	reg clk;
	reg reset;
	reg din;
	reg alpha;
	reg beta;
	wire dout;
	wire zeta;
	integer file;
	
	always
		begin : clk_gen
			clk = 1'b0;
			#5;
			clk = 1'b1;
		end
	
	always
		begin : din_gen
			din = 1'b0;
			#10;
			din = 1'b1;
			#10;
		end
	
	always
		begin : alpha_gen
			alpha = 1'b0;
			#10;
			alpha = 1'b1;
			#10;
		end
	
	always
		begin : beta_gen
			beta = 1'b0;
			#20;
			beta = 1'b1;
			#20;
		end
	
	initial
		begin: file_dump
			file = $fopen("$dsn/src/results.txt");
			$fmonitor(file, $time, " clk=%b reset=%b din=%b dout=%b alpha=%b beta=%b zeta=%b ", clk, reset, din, dout, alpha, beta, zeta);
		end
	
	initial
		begin : sim_control
			reset <= 1;
			#10 reset <= 0;
			#100 $fclose(file);
			$finish;
		end
	
	 
	test2 DUT (.alpha(alpha),
		.beta(beta),
		.zeta(zeta),
		.clk(clk),
		.reset(reset),
		.din(din),
		.dout(dout)
		);
endmodule

